RAM Sketch #1

Juno uses SRAM for its RAM.

Static RAM generally uses latches as storage elements and can therefore store data as long as power is supplied as opposed to DRAM which uses capacitors and cannot retain data for very long without the capacitors needing to be recharged. This makes SRAM simpler to use and hence why it has been selected.

DRAM can store much more data than SRAM but for the small amounts of memory required by Juno, measured in KB, this is not a constraint.

There are variations of SRAM including asynchronous or synchronous with burst features; and serial or parallel interfaces. The Juno uses asynchronous SRAM with parallel interface. Serial interface SRAM is for designs that need to minimise the number of connections. Parallel SRAM is easier to interface at the expense of requiring more connections.

The operation of asynchronous SRAM is not synchronised with the system clock therefore great care is required to ensure signals are applied in the right order. For example if write to memory is enabled before the address has stabilised the data will be written to random memory addresses with disastrous results.

Chip Enable - When asserted the SRAM chip is activated and responds to read and write commands. When not asserted the SRAM chip is in a dormant state and its internal logic is shutdown. The Address Decoder determines which device on the bus to enable based on the selected address.

Write Enable  - When asserted the SRAM continuously writes the data on the data bus to the given address.

Output Enable -  When asserted the SRAM continuously writes the data from memory to the data bus for the given address.

Basic Read Operation

The basic read operation is as follows. Note that Write Enable remains unasserted throughout this operation.
Step 1
- Place address on the address bus
- Enable chip select
- Enable output
- Receiving device such as a register latches the data output on rising clock edge

Basic Write Operation

The basic write operation is as follows. Note that Output Enable remains unasserted throughout this operation.
Step 1
- Place address on the address bus
- Enable chip select
- Place data on the data bus

Step 2
Now the address and data are stable the SRAM can be instructed to write to memory
-  Enable Write

Step 3
Having the written to SRAM writing must be disabled BEFORE the address or data is changed.  
- Disable write

Step 4
Having disabled writing it is now safe to change the address or data
- The address is changed/removed from the address bus
- Disable chip select
- Data is changed/removed from the data bus