Bypass capacitors

Precautions need to be taken to avoid the risk of erroneous digital transitions in digital circuits.When an IC output state changes short spikes are created on the ground and +ve lines and other ICs nearby may see these spikes as a logic change on their digital input resulting in disaster.

The best methods for protecting against this scenario are

1. Use a ground plane on the PCB (lower inductance and resistance means smaller spikes)
2. Use bypass capacitors liberally throughout the circuit

There are two types of bypass capacitors that I use in my designs

1. 0.1 uF (100nF) 25V ceramic disc capacitors across the +ve and GND pins of each IC (08-0235). Place one across the +ve and GND pins as close as possible.
2. Larger 10uF 25V tantalum capacitors to bypass the power supply on the pcb to provide a local reservoir of energy (11-0666 ). Place one across the power supply rails as close to the power connectors as possible.

Note for PCB designs use radial rather than axial capacitors as the leads come out of the same end and require less space on the pcb.

Use capacitors with a voltage rating at least double the expected voltage. For 5V CMOS digital the 25V capacitors above are what I had and capacitors with a lower voltage rating can be used.

8bit Register Design #1

Registers are constructed out of HC374 devices which are Octal positive-edge triggered D flip-flops with 3 state output that is non-inverting.

There are many variations of D type flip-flops.

• Octal means the 374 device has 8 D type flip-flops
• Positive Edge triggered means the register will latch the input on the rising edge of the clock. In order to ensure the register is only updated when required the 374 clock input will be connected to the output of an AND gate with the master clock signal and Reigster Write Enable signal as inputs. This will mask the clock signal unless register write is enabled.
• 3 state output means that the output will be in a high impedence state unless output is enabled. This allows multiple devices to share the same bus.
• Non-inverting output means the output is the same as the input. There are other versions of these devices that invert the ouput.

The 374 does not have a master reset therefore the value of the register will need to be initialied by some other means.

Logical design

The logical design below contains 2 8-bit registers based on 374 D flip-flops. The output of the register is placed on the bus by taking the Output Enable control LOW. The register input is enabled by taking the Load Enable control HIGH and the data will be latched on the next clock rising edge.

Microcode Sequencer Sketch #1

The microcode sequencer controls and synchronises the operation of all the components of Juno and is the heart of the CPU.

The microcode sequencer is loaded with the next instruction from the computer program and then steps through the microcode program associated with that instruction. A micro-code program is a very simple program that consists of a small number of micro-instructions and each micro-instruction enables one or more control signals that drive the other components of the CPU.

Data bus - The connection to the 8 bit data bus enables the next program instruction to be fetched from memory and loaded into the microcode sequencer.

Zero flag - The zero flag from the Control Register is used to implement conditional branches. The microcode sequencer checks the value of the zero flag to determine whether to implement the conditional.

Interrupt - If enabled the micro-code processor will run a microcode program to service the interrupt rather than load the next program instruction.

Interrupt # [0-n] - The identifier of the device that has raised the interrupt is is placed on the interrupt #lines.

Control Signals [0-n]  - The control signals are enabled according to the micro-instruction.

Reset - Enables the microcode sequencer to be reset to a known state on power on or reset.

Clk - The clock provides the timing signal to step through the microcode program.

RAM Sketch #1

Juno uses SRAM for its RAM.

Static RAM generally uses latches as storage elements and can therefore store data as long as power is supplied as opposed to DRAM which uses capacitors and cannot retain data for very long without the capacitors needing to be recharged. This makes SRAM simpler to use and hence why it has been selected.

DRAM can store much more data than SRAM but for the small amounts of memory required by Juno, measured in KB, this is not a constraint.

There are variations of SRAM including asynchronous or synchronous with burst features; and serial or parallel interfaces. The Juno uses asynchronous SRAM with parallel interface. Serial interface SRAM is for designs that need to minimise the number of connections. Parallel SRAM is easier to interface at the expense of requiring more connections.

The operation of asynchronous SRAM is not synchronised with the system clock therefore great care is required to ensure signals are applied in the right order. For example if write to memory is enabled before the address has stabilised the data will be written to random memory addresses with disastrous results.

Chip Enable - When asserted the SRAM chip is activated and responds to read and write commands. When not asserted the SRAM chip is in a dormant state and its internal logic is shutdown. The Address Decoder determines which device on the bus to enable based on the selected address.

Write Enable  - When asserted the SRAM continuously writes the data on the data bus to the given address.

Output Enable -  When asserted the SRAM continuously writes the data from memory to the data bus for the given address.

Basic Read Operation

The basic read operation is as follows. Note that Write Enable remains unasserted throughout this operation.
Step 1
- Place address on the address bus
- Enable chip select
- Enable output
- Receiving device such as a register latches the data output on rising clock edge

Basic Write Operation

The basic write operation is as follows. Note that Output Enable remains unasserted throughout this operation.
Step 1
- Place address on the address bus
- Enable chip select
- Place data on the data bus

Step 2
Now the address and data are stable the SRAM can be instructed to write to memory
-  Enable Write

Step 3
Having the written to SRAM writing must be disabled BEFORE the address or data is changed.  
- Disable write

Step 4
Having disabled writing it is now safe to change the address or data
- The address is changed/removed from the address bus
- Disable chip select
- Data is changed/removed from the data bus

Memory Map Sketch #1

Juno has a 16 bit address bus providing an address space of 64KB.

This address space is divided into 4KB blocks (defined by the 4 most significant bits) that the address decoder uses to select and therefore ensure only one device is driving the data bus at a time.

There are multiple devices connected to the data bus including ROM, RAM and IO devices. Typical ROM and RAM chips are much bigger than the 4KB block used and therefore multiple blocks will select the same  device. The reason for using 4KB blocks is that using a simple line decoder to implement the address decoder requires all memory blocks to be the same size and 4KB is more than sufficient space for mapping the IO devices into memory.

Memory Block	Dec	Hex	Memory Map	A[15-12]	A[11-0]
0	0	0	ROM	0000	xxxxxxxxxxxx
1	4096	1000		0001	xxxxxxxxxxxx
2	8192	2000		0010	xxxxxxxxxxxx
3	12288	3000		0011	xxxxxxxxxxxx
4	16384	4000		0100	xxxxxxxxxxxx
5	20480	5000		0101	xxxxxxxxxxxx
6	24576	6000		0110	xxxxxxxxxxxx
7	28672	7000	I/O	0111	xxxxxxxxxxxx
8	32768	8000	RAM	1000	xxxxxxxxxxxx
9	36864	9000		1001	xxxxxxxxxxxx
10	40960	A000		1010	xxxxxxxxxxxx
11	45056	B000		1011	xxxxxxxxxxxx
12	49152	C000		1100	xxxxxxxxxxxx
13	53248	D000		1101	xxxxxxxxxxxx
14	57344	E000		1110	xxxxxxxxxxxx
15	61440	F000		1111	xxxxxxxxxxxx
	65536	10000

NB a memory decoder for the above memory map can be implemented using a 4-to-16 line decoder to select devices e.g. 74HC138

More sophisticated memory decoders can be implemented using a memory device whose content maps addresses to devices allowing for much greater granularity. 

Even more sophisticated memory mapping techniques include bank swapping in which an external flag can be set to swap devices that are mapped to a specific part of the memory address space. This technique could be implemented in Juno using a bank swapping device that used IO commands to allow the selection between banks.

Much more sophisticated memory management techniques such as segementation, virtual memory and paging have not been considered.