8bit Register Design #1

Registers are constructed out of HC374 devices which are Octal positive-edge triggered D flip-flops with 3 state output that is non-inverting.

There are many variations of D type flip-flops.

• Octal means the 374 device has 8 D type flip-flops
• Positive Edge triggered means the register will latch the input on the rising edge of the clock. In order to ensure the register is only updated when required the 374 clock input will be connected to the output of an AND gate with the master clock signal and Reigster Write Enable signal as inputs. This will mask the clock signal unless register write is enabled.
• 3 state output means that the output will be in a high impedence state unless output is enabled. This allows multiple devices to share the same bus.
• Non-inverting output means the output is the same as the input. There are other versions of these devices that invert the ouput.

The 374 does not have a master reset therefore the value of the register will need to be initialied by some other means.

Logical design

The logical design below contains 2 8-bit registers based on 374 D flip-flops. The output of the register is placed on the bus by taking the Output Enable control LOW. The register input is enabled by taking the Load Enable control HIGH and the data will be latched on the next clock rising edge.