Register Design - Register Board One v2.1

The Register Board One has the following registers

• A - General purpose register
• IX(L) - Index Register low byte
• IX(H) - Index Register high byte
• SP(L) - Stack Pointer low byte
• SP(H) - Stack Pointer high byte
• Status Register- comprising ALU flags and CPU status flags

Changes from v1.x

• Updated to the v2.0 Architecture and the use of a dedicated common CPU bus for the CPU boards
• Compared to the v1.x register boards design the PC and MAR registers have been moved to their own separate CPU board.This was done due to the physical space constraints on a single board.

Schematics

The Register Board One design is split across four schematics

• Common CPU bus connector
• Control
• General Registers
• Status Register

Status Register

The Status Register holds four ALU operation output flags and two machine state flags. The four ALU operation flags are set when performing a mathematical operation.

• V - overflow
• C - Carry
• Z - Zero
• N - Negative

The Status Register contains two flags which indicate the system state

• Interrupts enabled - when set interrupts are enabled
• Supervisor mode - when set CPU is operating in supervisor mode

The Status Register is connected directly to the micro-code sequencer (and by a tri-state buffer to the Left Bus) and is used to implement instructions such as branching on conditions.

Status Register

The ALU flags are implemented using an Octal D type flip-flop with clk and master rest inputs (74HC273N). Unlike the 74HC574s used for the main registers the ALU flag does not require tri-stated outputs as the output is permanently required by the Micro Program Sequencer.

The ALU flags have a synchronous clear function which is controlled by /CPU_RESET.

The ALU flags are loaded by selecting the ALU_flag register via the control demux which causes the clk input to be strobed in the second half of the CPU clock cycle. The ALU flags can be loaded from either the ALU output or the Z bus selectable with by SEL_ALU_OR_Z. The intention of this design is that when a mathematical operation is being performed the ALU flags are loaded from the ALU output and when the current value of the flags needs to be preserved, for example by an interrupt service routine, they can be written to main memory and loaded back via the Z bus.

The Status flags are implemented using individual D-type flip-flops (74HC74). Individual flip-flops are required because the flags need to be set and cleared individually.

The status flags have synchronous clear function which is controlled by /CPU_RESET. The pre-set input is not used and is tied to VCC.

The status flags are set or cleared by instructing the ALU to ouput 1 or 0 on the Z bus and selecting which flag to load via the control demux which causes the strobes the flip-flop clk input to be strobed in the second half of the CPU clock cycle. This approach avoids the need for individual control signals to drive the flip-flop Preset and Clear inputs. The current value of the flags can be written to memory and loaded back via the Z bus.

Registers

The general registers are implemented using octal D-type flip-flops (74HC574). Inputs are connected to the Z Bus (ALU output bus) and the tri-state outputs are connected to the Left Bus. The schematic for the general registers is shown below.

Gerneral Registers

The register clk inputs are connected to a control decoder which strobes the selected register clk input in the second half of the clk cycle when the CPU Inverted Clock goes high.

The register /OE inputs are connected to a control decoder which asynchronously sets the selected output low. The desired register is selected at the beginning of the CPU clock cycle and being asynchronous there may be glitches in the output onto the Left Bus as the demux input select settles. For this reason the value on the Left bus is latched during the second half of the clock cycle.

Control

The selection of which register to load from the Z bus is controlled via a 3-to-8 line decoder (74HC238). Output 0 unconnected and can be used to load no register when selected. The selected output is strobed High in the second half of the CPU clock cycle when the CPU Inverted Clock goes high.

The selection of which register to output onto the Left bus is controlled via an inverting 3-to-8 decoder  (74HC138). Output 0 is not connected.

Control

Common CPU bus connector

 

Common bus connector

PCB

The PCB board is shown below

PCB board

Parts List

Exported from GeneralRegister8.brd at 04/01/2015 21:53:25

EAGLE Version 7.2.0 Copyright (c) 1988-2014 CadSoft

Assembly variant:

Part         Value          Package      Library  Position (inch)       Orientation

/OE          74HC138N       DIL16        74xx-eu  (2.3 3.5)             R180
A            74HC574N       DIL20        74xx-eu  (3.1 2.5)             R270
ALU_FLAGS    74HC273N       DIL20        74xx-eu  (0.75 0.95)           R90
ALU_OR_Z     74HC157N       DIL16        74xx-eu  (2.65 0.9)            R90
C1           0.1uF          C050-030X075 rcl      (3.15 3.1)            R180
C2           0.1uF          C050-030X075 rcl      (2.7 3.1)             R180
C3           0.1uF          C050-030X075 rcl      (2.25 3.1)            R180
C4           0.1uF          C050-030X075 rcl      (1.8 3.1)             R180
C5           0.1uF          C050-030X075 rcl      (1.35 3.1)            R180
C6           10uF           E5-5         rcl      (3.85 0.25)           R180
C7           0.1uF          C050-030X075 rcl      (2.35 0.65)           R90
C8           0.1uF          C050-030X075 rcl      (0.7 3.1)             R180
C9           0.1uF          C050-030X075 rcl      (2.8 3.45)            R90
C10          0.1uF          C050-030X075 rcl      (0.45 0.6)            R90
C11          0.1uF          C050-030X075 rcl      (2.35 1.65)           R90
C12          0.1uF          C050-030X075 rcl      (1.5 0.55)            R180
IC3          74HC244N       DIL20        74xx-eu  (0.65 2.5)            R270
IX(H)        74HC574N       DIL20        74xx-eu  (1.3 2.5)             R270
IX(L)        74HC574N       DIL20        74xx-eu  (1.75 2.5)            R270
LD           74HC238N       DIL16        paul     (1.85 1.7)            R180
SP(H)        74HC574N       DIL20        74xx-eu  (2.2 2.5)             R270
SP(L)        74HC574N       DIL20        74xx-eu  (2.65 2.5)            R270
STATUS_FLAGS 74HC74N        DIL14        74xx-eu  (1.9 0.85)            R90
X1           MAB64          MAB64        con-vg   (4.15 1.95)           R0

Architecture v2.0

Version 2.x of Juno incoporates yet more major changes to the physical architecture of the system. The primary change being the splitting of the common system bus back plane, into which all the cards connect, into two seperate busses

• Common CPU bus - into which all the CPU cards connect, and
• Common external bus - into which all external system boards connect

The v1.x Architecture had a single common bus based on a DIN41612 64 pin connector shared by all cards but this was not enough pins for all the required signals.

Common CPU bus

The common CPU bus carries signals which are internal to the CPU and each CPU board connects to the common CPU bus via a single DIN41612 64 pin connector. The signals carried on the common CPU bus include

• Left Bus (ALU left input)
• Right Bus (ALU right input)
• CPU Z Bus (ALU output)
• CPU control signals e.g. load register etc
• Status Register - ALU flags V, C, Z & N and the status flags Interrupts Enabled and Supervisor Mode 
• CPU clocks - non-inverted and inverted clock signals
• CPU reset
• Power
• misc. board to board signals as required 

Common External bus

The common External bus carries signals which are external to the CPU and each external board connects to the bus via a single DIN41612 64 pin connector. The signals carried on the common external bus include

• Address bus
• Data bus
• Control signals e.g. read, write
• External clocks 
• Power
• Interrupts