Changes from v0.x
Version 1.x of the Juno boards incorporates some major changes to the physical architecture of the system including:- Larger Eurocard PCB board format (100mm x 160mm)
- Use of a DIN41612 connectors
- Use of a common system bus back plane into which all cards connect
but no attempt has been made to be compatible with it.
Register Board v1.1 Architecture
The v1.1 Register Board has the following registers- A - General purpose register
- IX(L) - Index Register low byte
- IX(H) - Index Register high byte
- SP(L) - Stack Pointer low byte
- SP(H) - Stack Pointer high byte
- PC(L) - Program Counter low byte.
- PC(H) - Program Counter high byte.
- MAR(L) - Memory Address Register low byte. Not visible to the programmer.
- MAR(H) - Memory Address Register high byte. Not visible to the programmer.
- Status Register- ALU flags and status flags
Status Register
The Status Register holds four ALU operation output flags and two machine state flags. The four ALU operation flags are set when performing a mathematical operation.- V - overflow
- C - Carry
- Z - Zero
- N - Negative
- Interrupts enabled - when set interrupts are enabled
- Supervisor mode - when set CPU is operating in supervisor mode
Schematics
The Register Board design is split across four schematics- Registers
- Program Counter
- ALU flags and Status
- Connections
Registers
The schematic for the main registers is shown below.
The register clk inputs are connected to a 4-to-16 Demux which strobes the selected register clk input in the second half of the clk cycle (when the main Clk goes low). This is achieved by tieing the Demux's inhibit input to the main clk so that during the first half of the clock cycle inhibit is high and the Demux's outputs are forced Low. When Inhibit goes low the Demux's outputs are enabled and the selected register clk strobed and the input latched.
The register /OE inputs are connected to a 3-to-8 inverting demux which asynchronously sets the selected output low. The desired register is selected at the beginning of the clock cycle and being asynchronous there may be glitches in the output onto the Left Bus as the demux input select settles. For this reason the value on the Left bus is latched during the second half of the clock cycle.
An Octal Buffer line driver (74HC244N) is used to place the value on the Left Bus onto the Data Bus for register read operations. At all other times the 244N outputs are tri-stated.
Program Counter
The schematic for the program counter is shown below.
The Program Counter has a synchronous clear function which is controlled by /RESET. The Program Counter clk inputs are connected to the main inverted CPU clock to provide a positive rising edge in the second half of the clock cycle.
Taking INC_PC high causes the Program Counter to synchronously increment the PC on the rising edge of the clk.
Taking LD_PC(L) or LD_PC(H) high causes the low/high byte of the Program Counter to synchronously parallel load from the Z bus on the rising edge of the clk. The LD_PC(L) and LD_P(H) inputs are inverted as the counter parallel enable input (/PE) is active low.
The value of the Program Counter is placed on the Address Bus by taking /OE_PC_ABUS low which enables the outputs of the address bus Octal Buffer line drives.
The High or Low value of the Program Counter is placed on the Left Bus by /OE_PC(L) or /OE_PC(H) being low. Externally these are selected via the 3-to-8 inverting demux.
ALU and Status flags
The schematic for the ALU and status flags is shown below.
The ALU flags are implemented using an Octal D type flip-flop with clk and master rest inputs (74HC273N). Unlike the 74HC574s used for the main registers the ALU flag does not require tri-stated outputs as the output is permanently required by the Micro Program Sequencer.
The ALU flags have a synchronous clear function which is controlled by /RESET.
The ALU flags are loaded by selecting the ALU_flag register via the 4-to-16 demux which strobes the clk input in the second half of the clock cycle. The ALU flags can be loaded from either the ALU output or the Z bus selectable with by SEL_ALU_OR_Z. The intention of this design is that when a mathematical operation is being performed the ALU flags are loaded from the ALU output and when the current value of the flags needs to be preserved, for example by an interrupt service routine, they can be written to main memory and loaded back via the Z bus.
The Status flags are implemented using individual D-type flip-flops (74HC74). Individual flip-flops are required because the flags need to be set and cleared individually.
The status flags have synchronous clear function which is controlled by /RESET. The pre-set input is not used and is tied to VCC.
The status flags are set or cleared by first selecting which one to load via the 4-to-16 demux which strobes the selected flag's clk input in the second half of the clock cycle and loads the flip-flop from the Z bus (Z4 for Interrupt Enabled and Z5 for Supervisor Mode). Set or Reset is achieved by instructing the ALU to output all 0's and 1's. The current value of the flags can be written to memory and loaded back via the Z bus.
/OE_Status places the contents of the ALU and Status flags on the Left Bus.
Connections
The register board external connections are shown below
