The basic mode of operation is as follows with the inverted clock being used to latch the output of each microcode operation.
- On the rising CLK the microcode counter is incremented and the next microcode operation is read from microcode memory. The control signals start flowing out into the CPU.
- During CLK high period the combinational logic settles down to a stable valid state.
- On the rising CLK_inv the calculated output is latched.
- During the CLK Low period nothing of interests happens.
To write to memory two full cycles are required :
Cycle 1 - during first half of the cycle the memory location is addressed and data value placed on the data bus. During the second half, writing to memory is enabled and the memory written
- On the rising CLK the control signals start flowing out into the CPU
- During the CLK high period the memory location is set on the Address Bus and the value on the Data Bus. The memory write control signal is taken High. The memory write control signal is NAND'd with CLK_inv to drive the memory /WE signal.
- Rising CLK_inv / falling CLK
- During CLK_INV high the memory /WE is taken low and the value on the Data bus is written to the selected memory location whilst /WE remains low.
- On the rising CLK the control signals start flowing out into the CPU
- During the CLK high period the addressed memory location is held on the Address Bus and the value is held on the Data Bus. The memory control signal is taken low which in turn takes the memory /WE signal high and disables the write.
- During the rest of the cycle nothing of interest happens
Fast SRAM has a /WE pulse requirement of circa 20ns. Given the target Juno clock is in the single digit MHz range taking /WE low for half a clock cycle will far exceed this
1/1MHz = 1,000 nanoseconds
1/10MHz = 100 nanoseconds
1/100MHz = 10 nanoseconds
