Register Design v1.1

Changes from v0.x

Version 1.x of the Juno boards incorporates some major changes to the physical architecture of the system including:

• Larger Eurocard PCB board format (100mm x 160mm)
• Use of a DIN41612 connectors 
• Use of a common system bus back plane into which all cards connect

The new physical architecture is inspired by 1970s systems based on the S-100 bus such as the Altair 8800
but no attempt has been made to be compatible with it.

Register Board v1.1 Architecture

 The v1.1 Register Board has the following registers

• A - General purpose register
• IX(L) - Index Register low byte
• IX(H) - Index Register high byte
• SP(L) - Stack Pointer low byte
• SP(H) - Stack Pointer high byte
• PC(L) - Program Counter low byte. 
• PC(H) - Program Counter high byte.
• MAR(L) - Memory Address Register low byte. Not visible to the programmer.
• MAR(H) - Memory Address Register high byte. Not visible to the programmer.  
• Status Register- ALU flags and status flags

 Status Register

The Status Register holds four ALU operation output flags and two machine state flags. The four ALU operation flags are set when performing a mathematical operation.

• V - overflow
• C - Carry
• Z - Zero
• N - Negative

The Status Register contains two flags which indicate the system state

• Interrupts enabled - when set interrupts are enabled
• Supervisor mode - when set CPU is operating in supervisor mode

The Status Register is connected directly to the micro-code sequencer (and by a tri-state buffer to the Left Bus) and is used to implement instructions such as branching on conditions.

Schematics

The Register Board design is split across four schematics

• Registers
• Program Counter
• ALU flags and Status
• Connections

 Registers

The schematic for the main registers is shown below.

The main registers are implemented using octal D-type flip-flops (74HC574). Inputs are connected to the Z Bus (ALU output bus) and the tri-state outputs are connected to the Left Bus.

The register clk inputs are connected to a 4-to-16 Demux which strobes the selected register clk input in the second half of the clk cycle (when the main Clk goes low). This is achieved by tieing the Demux's inhibit input to the main clk so that during the first half of the clock cycle inhibit is high and the Demux's outputs are forced Low.  When Inhibit goes low the Demux's outputs are enabled and the selected register clk strobed and the input latched.

The register /OE inputs are connected to a 3-to-8 inverting demux which asynchronously sets the selected output low. The desired register is selected at the beginning of the clock cycle and being asynchronous there may be glitches in the output onto the Left Bus as the demux input select settles. For this reason the value on the Left bus is latched during the second half of the clock cycle.

An Octal Buffer line driver (74HC244N) is used to place the value on the Left Bus onto the Data Bus for register read operations. At all other times the 244N outputs are tri-stated. 

Program Counter

The schematic for the program counter is shown below.

The 16-bit Program Counter is implemented using four 4-bit pre-settable counters (74HC161). Inputs are connected to the Z Bus (ALU output) and the outputs are connected to both the Left Bus and Address Bus via Octal Buffer line drivers.

The Program Counter has a synchronous clear function which is controlled by /RESET. The Program Counter clk inputs are connected to the main inverted CPU clock to provide a positive rising edge in the second half of the clock cycle. 

Taking INC_PC high causes the Program Counter to synchronously increment the PC on the rising edge of the clk.

Taking LD_PC(L) or LD_PC(H) high causes the low/high byte of the Program Counter to synchronously parallel load from the Z bus on the rising edge of the clk. The LD_PC(L) and LD_P(H) inputs are inverted as the counter parallel enable input (/PE) is active low.

The value of the Program Counter is placed on the Address Bus by taking /OE_PC_ABUS low which enables the outputs of the address bus Octal Buffer line drives.

The High or Low value of the Program Counter is placed on the Left Bus by /OE_PC(L) or /OE_PC(H) being low. Externally these are selected via the 3-to-8 inverting demux.

ALU and Status flags

The schematic for the ALU and status flags is shown below.

The ALU flags are implemented using an Octal D type flip-flop with clk and master rest inputs (74HC273N). Unlike the 74HC574s used for the main registers the ALU flag does not require tri-stated outputs as the output is permanently required by the Micro Program Sequencer.

The ALU flags have a synchronous clear function which is controlled by /RESET. 

The ALU flags are loaded by selecting the ALU_flag register via  the 4-to-16 demux which strobes the clk input in the second half of the clock cycle. The ALU flags can be loaded from either the ALU output or the Z bus selectable with by SEL_ALU_OR_Z. The intention of this design is that when a mathematical operation is being performed the ALU flags are loaded from the ALU output and when the current value of the flags needs to be preserved, for example by an interrupt service routine, they can be written to main memory and loaded back via the Z bus.

The Status flags are implemented using individual D-type flip-flops (74HC74). Individual flip-flops are required because the flags need to be set and cleared individually.

The status flags have synchronous clear function which is controlled by /RESET. The pre-set input is not used and is tied to VCC.

The status flags are set or cleared by first selecting which one to load via the 4-to-16 demux which strobes the selected flag's clk input in the second half of the clock cycle and loads the flip-flop from the Z bus (Z4 for Interrupt Enabled and Z5 for Supervisor Mode). Set or Reset is achieved by instructing the ALU to output all 0's and 1's. The current value of the flags can be written to memory and loaded back via the Z bus.

/OE_Status places the contents of the ALU and Status flags on the Left Bus.

Connections

The register board external connections are shown below

DIN 41612

DIN 41612 is a standard for connectors that are widely used in rack systems

A connector can have one, two or three rows of contacts, which are labelled as rows a, b and c. Two row connectors may use rows a+b or rows a+c. The connectors may have 16 or 32 columns, which means that the possible permutations allow 16, 32, 48, 64 or 96 contacts. The rows and columns are on a 0.1 inch (2.54 mm) grid pitch. [ref wikipedia]. Connectors can also be straight or right-angled. 

Manufactures offer many different types of 41612 which can make finding a socket and plug combination that match frustrating on the big electronic parts websites.

I eventually found the following 64 way, a+b, 2.54mm, B shell sockets and plugs at toby.co.uk which appear great value.

Part No	Quantity	Price
B shell 2 row sockets
405AF-64FSSAAB4	10	£9.50
B shell 2 row plugs
405AF-64MSRAAE4	10	£7.50

The data sheet gave the following physical sizing for the right angled B shell plugs

• Distance between screw centres = 88.90 (~3.5 inch)
• Length = 94mm (~3.7 inch)

and the following for the vertical B shell sockets

•  Distance between screw centre = 90mm (~5.55 inch)
• Length = 95 mm (~3.7 inch)

Looking at the EagleCAD parts library I found the part MAB64 in the con-vg library which seems to match the plug and MAB64Q the socket therefore I have gone ahead and order 10 of each.

Clock & Timings

The Juno CPU has two clocks CLK and CLK_inv which is CLK inverted.

The basic mode of operation is as follows with the inverted clock being used to latch the output of each microcode operation.

1. On the rising CLK the microcode counter is incremented and the next microcode operation is read from microcode memory. The control signals start flowing out into the CPU.
2. During CLK high period the combinational logic settles down to a stable valid state. 
3. On the rising CLK_inv the calculated output is latched.
4. During the CLK Low period nothing of interests happens.  

To write to memory two full cycles are required :

Cycle 1 - during first half of the cycle the memory location is addressed and data value placed on the data bus. During the second half, writing to memory is enabled and the memory written

1.  On the rising CLK the control signals start flowing out into the CPU
2. During the CLK high period the memory location is set on the Address Bus and the value on the Data Bus. The memory write control signal is taken High. The memory write control signal is NAND'd with CLK_inv to drive the memory /WE signal.
3. Rising CLK_inv / falling CLK
4. During CLK_INV high the memory /WE is taken low and the value on the Data bus is written to the selected memory location whilst /WE remains low.

Cycle 2 - the memory location and data value are maintained and the writing to memory action is stopped by taking setting the memory write signal Low (CLK_INV going low will also disable the writing action)

1. On the rising CLK the control signals start flowing out into the CPU
2. During the CLK high period the addressed memory location is held on the Address Bus and the value is held on the Data Bus. The memory control signal is taken low which in turn takes the memory /WE signal high and disables the write.
3. During the rest of the cycle nothing of interest happens

Fast SRAM has a /WE pulse requirement of circa 20ns.  Given the target Juno clock is in the single digit MHz range taking /WE low for half a clock cycle will far exceed this

1/1MHz = 1,000 nanoseconds
1/10MHz = 100 nanoseconds
1/100MHz = 10 nanoseconds

Status Register design v0.1

The status register consists of 4 ALU operation flags (V, C, Z & N) and two status flags, Interrupt Enable & Supervisor Mode.

The 4 ALU flags are stored in an octal D-type flip-flop 74HC273, which has common CLK and CLR inputs. The two status flags are stored in two D-type flip-flops from a 74HC74 and have individual inputs. 

When the status flag is initialised all the bits are set to zero. To enable interrupts the Interrupt Enable flag needs to be set. Setting the Operation Supervisor Mode bit indicates the CPU is operating in supervisor mode.

Inputs & Ouputs

The inputs and outputs to the Status Register are as follows:

Inputs

• RESET_LOW when low asynchronously clears the 4 ALU flags and two status flags. 
• ALU_FLAG_IN (V, C, Z, N) are connected to the ALU flag outputs on the ALU's Shifter board.
• SEL_ALU_OR_Z selects between ALU_FLAG_IN or Z bus (bits 0..3) as input to the ALU flag register. Low selects ALU_FLAG_IN as the input
• L_ALU_FLAGS when high loads the ALU Flags from the selected input
• L_ENABLEINT when pulsed high loads the Supervisor mode flag with the current value of the 4th bit of the Z bus
• L_SUPMODE when pulsed high loads the Enable interrupt flag with the current value of the 5th bit of the Z bus
• E_STATUS_REG when low outputs the Status Register onto the Left Bus
• Z bus -  bit 0 = V, 1 = C, 2 = Z, 3 = N, 4 = enable interrupt, 5 = supervisor mode

Outputs

• SEQ_STATUS directly outputs the contents of the Status Register flags to the Microcode sequencer. The Carry flag is also sent to the ALU.
• Left_bus - bit 0 = V, 1 = C, 2 = Z, 3 = N, 4 = enable interrupt, 5 = supervisor mode

Operational usage

To load the ALU flags when conducting a mathematical operation set SEL_ALU_OR_Z to low to select the input from the ALU and pulse L_ALU_FLAGS high to load the flags.

To set or clear the Interrupt Enable flag set bit 4 on the Z bus and pulse the L_ENABLEINT high to load the flag. To set or clear the Supervisor Mode flag use bit 5. 

To ouput the Status Register to the left bus, for example as part of an operation to save to memory, set E_STATUS_REG low. At all other times the High Impedence state should be selected by setting E_STATUS_REG high. 

To load the Status Register from the  Z bus, for example as part of an opertation to load from memory, set SEL_ALU_OR_Z high to select the input from the Z Bus and pulse L_ALU_FLAGS, L_SUPMODE and L_ENABLEINT high.

Circuit Schematic

Status Register v0.1 schematic

PCB Board Layout

Status Register PCB layout

 

Parts list

Part            Value          Device          Package      Library  Sheet

/OE_REG                        PINHD-1X8       1X08         pinhead  1
ALU-LBUS                       PINHD-1X8       1X08         pinhead  1
ALU-RBUS                       PINHD-1X8       1X08         pinhead  1
ALU-ZBUS                       PINHD-1X8       1X08         pinhead  1
ALU_FLAG_IN                    PINHD-1X4       1X04         pinhead  1
C1              0.1uF          C-EU050-030X075 C050-030X075 rcl      1
C2              0.1uF          C-EU050-030X075 C050-030X075 rcl      1
C13             0.1uF          C-EU050-030X075 C050-030X075 rcl      1
C14             0.1uF          C-EU050-030X075 C050-030X075 rcl      1
C15             0.1uF          C-EU050-030X075 C050-030X075 rcl      1
C16             0.1uF          C-EU050-030X075 C050-030X075 rcl      1
C17             10uF           CPOL-EUE5-5     E5-5         rcl      1
DBUS                           PINHD-1X8       1X08         pinhead  1
IC1             74HC244N       74HC244N        DIL20        74xx-eu  1
IC2             74HC244N       74HC244N        DIL20        74xx-eu  1
IC3             4515N          4515N           DIL24-6      45xx     1
IC4             4514N          4514N           DIL24-6      45xx     1
IC7             74HC273N       74HC273N        DIL20        74xx-eu  1

 

How to make crimp connectors

In this post I will show you how to make your own crimp connectors such as those from proto-pic. These allow you to create your own 0.1" cables with the right number of pins and cable length for your project.

To create your own cables you will need

• 0.1" (2.54mm) crimp connector housings. These come in a range of different pin sizes each 1x2 pin, 1x4 pin etc
• Female crimp pins for 0.1" housing. One for the end of each wire but allow for 10% wastage when ordering. 
• Crimping tool. The 0.1-1.0 mm² Capacity, 16-28 AWG crimping tool sold by proto-pic worked fine for me.
• Wire stripper
• Roll of wire

Step 1 - strip the wire

• Cut the individual wires to length from the roll of wire
• Trim the individual wires to the same length to make a neat and tidy cable
• Strip 2-3mm from the end of each wire. 

When stipping the wire you want the length to be so that when the wire is inserted into the pin the PVC is in the area highlighted in black in the photo below; the stipped wire is in the area shown in red and it MUST NOT extend into the area shown in orange. The stripped wire in the photo is actually a bit too long and I cut a fraction off the end so that it did not extend out of the red area.

Step 2 - placing the pin in the crimping tool

Crimping the pin is a fiddly process but if you follow these steps you should be successful. The first step is to place the pin (without the wire) into the crimping tool and squeeze down to hold the pin in place but not  squash it.

It is critical that the pin is placed in the crimping tool correctly and understanding what the crimping process does will make it easier understand how the pin should be placed correctly.

The crimping tool folds over the two sets of edges to firmly hold the wire in place. The first set of edges fold over and clamp onto the PVC to secure the wire in place, highlighted in black in the picture. The second set of edges fold over and clamp onto the stripped wire to form the electrical connection, highlighted in red. The box shaped part of the pin, the area in orange, MUST NOT be squashed when crimping or it will destroy the pin.

The edges that fold over onto the PVC do not fold as far as the folds over the stripped wire and if you look at your crimping tool you will see that the teeth are shaped so that one half gets squashed (crimped) more than the other. It is critical to ensure that the pin is placed in the crimping tool the right way around in this respect.



Place the pin into the crimping tool, with the folds pointing upwards, and squeeze until the pin is held in place but not squashed and ensure the box part sticking safely out of the side.

Step 3 - insert the wire into the pin

Securely holding the pin in place by keeping pressure on the crimping tool handle feed the wire into the pin. The PVC part should be just inside so that it is under the first set of folds. If you see the stripped wire sticking out of the other end into the box part of the pin then you have inserted it too far and need to pull it back slightly.

Step 4 - crimp the pin

Once the wire is in the right position squeeze the handle fully to crimp the wire.

If it has been done correctly the first set of folds are securely clamped onto the PVC (area in black) ; the second folds are clamped onto stripped wire (area in red) and non wire is sticking into the box-end and the box is not squashed or damaged.

Step 5 - insert the pin into the housing

With the fiddly part complete the final step is to push the pin into the housing until it clicks in place.



Good luck!

Register Design v0.2

Changes from v0.1

In developing the Register Board schematic and PCB the design has undergone a change from v0.1 in that the Temp register has been removed. This greatly simplified the design and eliminated a number of ICs as the Internal Data Bus can now be connected directly to the ALU right input. The Temp register was originally intended to optimise a few operations such as adding A to itself by avoiding a memory read/write operation. On balance the simplification in complexity will hopefully outweigh the loss.

Register Board v0.2 Design

The following drawing shows the Register design for the Juno. Juno has the following registers:

• A - General purpose register
• B - General purpose register
• IX(L) - Index Register low byte
• IX(H) - Index Register high byte
• SP(L) - Stack Pointer low byte
• SP(H) - Stack Pointer high byte
• PC(L) - Program Counter low byte. 
• PC'(L) - Copy of the Program Counter low byte. Connected to the Address bus.
• PC(H) - Program Counter high byte.
• PC'(H) - Copy of the Program Counter high byte. Connected to the Address bus.
• MAR(L) - Memory Address Register low byte. Not visible to the programmer.
• MAR(H) - Memory Address Register high byte. Not visible to the programmer.  
• Status Register

Juno Register Design v0.2

 Status Register

The Status Register contains the following four ALU operation flags which are set when performing a mathematical operation

• V - overflow
• C - Carry
• Z - Zero
• N - Negative

The Status Register also contains two flags which can be set by ORing the Status Register

• Interrupts disabled - when set interrupts are disabled. 
• Reserved (for future use)

The Status Register is connected directly to the micro-code sequencer (and by a tri-state buffer to the Left Bus) and is used to implement instructions such as branching on conditions.

EagleCAD Board Design

The Eagle CAD schematic can be downloaded here and the PCB board here.

There was not enough space on the PCB to include the Status Register components therefore this will be placed on its own dedicated PCB. 

Register Board v0.2 PCB

EagleCAD PCB settings

• Text - size 0.04, ratio 10%, font = vector
• Mounting holes - 3.0mm mounting holes. Top left 0.20, 2.95. Bottom Right 3.75, 0.20
•  Signal Net class - width 0.25mm, drill 0.25mm, clearance 0.25mm
• Power Net class - width 0.3mm, drill 0.3mm, clearance 0.3mm
• Signal 0.012inch (selected from EagleCAD's defaults)
• Power 0.016inch (selected from EagleCAD's defaults. Slightly bigger than the 0.3mm minimum)
• Ground plane on top and bottom. Isolation on polygon set to 0.012

Parts list

Part      Value          Package      Library  Position (inch)       Orientation

/OE_AB                   1X02         pinhead  (3.85 1.55)           R90
/OE_REG                  1X09         pinhead  (1.9 0.1)             R0
A         74HC574N       DIL20        74xx-eu  (0.4 0.9)             R90
ABUS0..7                 1X08         pinhead  (0.9 3.05)            R0
ABUS8..15                1X08         pinhead  (3.85 2.35)           R90
ALU-ZBUS                 1X08         pinhead  (3.85 0.9)            R90
B         74HC574N       DIL20        74xx-eu  (0.85 0.9)            R90
C1        0.1uF          C050-030X075 rcl      (0.5 0.2)             R270
C2        0.1uF          C050-030X075 rcl      (3.05 1.65)           R0
C3        0.1uF          C050-030X075 rcl      (1.7 1.65)            R0
C5        0.1uF          C050-030X075 rcl      (2.15 1.65)           R0
C6        0.1uF          C050-030X075 rcl      (0.8 0.25)            R0
C7        0.1uF          C050-030X075 rcl      (3.4 0.2)             R270
C8        0.1uF          C050-030X075 rcl      (1.25 0.25)           R0
C9        0.1uF          C050-030X075 rcl      (1.7 0.25)            R0
C10       0.1uF          C050-030X075 rcl      (2.15 0.25)           R0
C11       0.1uF          C050-030X075 rcl      (2.6 0.25)            R0
C12       0.1uF          C050-030X075 rcl      (3.05 0.25)           R0
C15       0.1uF          C050-030X075 rcl      (2.6 1.65)            R0
C17       10uF           E5-5         rcl      (1.65 3.05)           R180
IX(H)     74HC574N       DIL20        74xx-eu  (1.75 0.9)            R90
IX(L)     74HC574N       DIL20        74xx-eu  (1.3 0.9)             R90
LBUS                     1X08         pinhead  (0.1 0.9)             R90
L_REG                    1X13         pinhead  (0.1 2.1)             R90
MAR(H)    74HC574N       DIL20        74xx-eu  (3.1 2.35)            R90
MAR(L)    74HC574N       DIL20        74xx-eu  (2.2 2.35)            R90
PC'(H)    74HC574N       DIL20        74xx-eu  (2.65 2.35)           R90
PC'(L)    74HC574N       DIL20        74xx-eu  (1.75 2.35)           R90
PC(H)     74HC574N       DIL20        74xx-eu  (2.65 0.9)            R90
PC(L)     74HC574N       DIL20        74xx-eu  (2.2 0.9)             R90
PWR                      1X02         pinhead  (2 3.05)              R0
SP(H)     74HC574N       DIL20        74xx-eu  (3.55 0.9)            R90
SP(L)     74HC574N       DIL20        74xx-eu  (3.1 0.9)             R90