Micro code controller

Each CPU instruction such as "LDA <address>" is implemented as a sequence of micro code operations. 

Each micro code operation sets the CPU control signals high or low and holds them for a clock cycle before moving to the next micro code operation in the sequnce. 

These CPU control signals are encoded as data in ROM chips. A '1' sets the control signal high and '0' sets the control signal low. 

The ROM contents are addressed using an 8-bit address, 4 bits for the instruction being executed plus 4 bits for the step in the micro code sequence. Therefore, the Juno PC supports 16 CPU instructions and each instruction can be up to 16 steps in length.

To support the number of control signals needed several 8-bit ROM chips are used. 

Instruction Register

The current instuction being executed is held in the 4-bit Instruction Register (IR). Each instuction has a unique number between 0 and 15.For example, the NOP instuction is instuction 0.

At the start of every instruction the Program Counter (PC) register must hold the address of the instruction to be executed and the first step of the micro code sequence is to load the IR with the instruction pointed to by PC. 

The micro code controller will then step through the sequence of operations for the instruction. 

NB on starting a new instruction IR will actually hold the previous instruction and execute step 0 which will load IR with the instruction at address PC.

Micro code step sequencer

The micro code step sequencer is implemented using a 4-bit counter. To start a new instruction the counter is reset to zero by the previous instruction. The counter is then incremented by the clock until it is reaches the last step in the sequence. The last step in sequence must reset the counter to zero using the uCounterRest control signal to start the next intruction.

The counter is implemented using a 74HC393 counter which features a clock input that increments the counter on a falling edge. A clock cycle is therefore from one falling edge to the next and the control signals are held for the duration of this clock cycle. 

The CPU control signals for load, or write, operations are logically AND with the clock signal so that control signal goes positive half way through the clock cycle. For example, registers are implemented using postive edge triggered chips such as the 74HC574.

This control sequence ensures there is time for the control signals and digital circuits to stabalise before performing the load / write actions. 

Clock and basic timing operation

A clock signal is a periodic signal that switches between high and low and is used to coordinate the actions of digital circuits.

A clock cycle is the time between two rising edges and consists of

• A - a fast low to high rising edge  
• B - a high state
  
• C - a fast high to low falling edge
• D - a low state
  

Sequential digital circuits can be designed to be 

• tiggered by either a rising or falling edge or 
• to be active during a high or low level
  

In this way the operation of a CPU can be contolled and co-ordinated. For example, to load a register with the contents from a memory address location the clock can co-ordinate the operation as follows:

1. on the falling edge the CPU 'micro code controller' enables the output of the Memory Address register and the memory address starts to flow over the address bus to the memory chip. 
   
2. The memory chip outputs the addressed data onto the data bus
3. Initially, both the memory address and data output are unstable but quickly stabalise and the data on the data bus becomes valid
   
4. Next, on the rising clock edge the CPU 'micro code controller' triggers the register to load the now valid data presented on the data bus
   

To achieve this timing the CPU control signals for load, or write, operations are logically AND with the clock signal so that control signal goes positive half way through the clock cycle. For example, registers are implemented using postive edge triggered chips such as the 74HC574.