Clock and basic timing operation

A clock signal is a periodic signal that switches between high and low and is used to coordinate the actions of digital circuits.

A clock cycle is the time between two rising edges and consists of

• A - a fast low to high rising edge  
• B - a high state
  
• C - a fast high to low falling edge
• D - a low state
  

Sequential digital circuits can be designed to be 

• tiggered by either a rising or falling edge or 
• to be active during a high or low level
  

In this way the operation of a CPU can be contolled and co-ordinated. For example, to load a register with the contents from a memory address location the clock can co-ordinate the operation as follows:

1. on the falling edge the CPU 'micro code controller' enables the output of the Memory Address register and the memory address starts to flow over the address bus to the memory chip. 
   
2. The memory chip outputs the addressed data onto the data bus
3. Initially, both the memory address and data output are unstable but quickly stabalise and the data on the data bus becomes valid
   
4. Next, on the rising clock edge the CPU 'micro code controller' triggers the register to load the now valid data presented on the data bus
   

To achieve this timing the CPU control signals for load, or write, operations are logically AND with the clock signal so that control signal goes positive half way through the clock cycle. For example, registers are implemented using postive edge triggered chips such as the 74HC574.