Architecture sketch #3

The third version of the Juno architecture. The following changes have been made:

- all program visible registers have been moved to the ALU left bus.

- a temp register which will be invisible to programs has been added to the right ALU bus.

Moving the registers has greatly simplified the bus design and made the instruction set more regular and therefore hopefully less error prone to construct.

The inclusion of a temp register enables register to register operations to be implemented in microcode e.g. A = A + B can be implemented in microcode by first copying B to temp and then performing A = A + temp. This is quicker and requires fewer program instructions than writing B to memory and then adding to A.

ALU sketch #1

The Juno ALU is an 8 bit design supporting 8 functions selected via a 3 bit operation selector control. 

The ALU takes its input from left and right buses and places the calculated output on the ALU's out bus. The output is not synchronised to the clock and therefore follows the inputs and will fluctuate for a period as both the inputs and internal logic stabilise. 

The ALU additionally outputs a number of flags indicating carry, overflow, zero, negative conditions that are stored in the control register

Operation select - the ALU supports 8 mathematical and logical functions selected by the 3 bit operation select control lines.

- AND : logical AND

- OR : logical OR

- NOT : logical NOT

- XOR : logical XOR

- CMP : logical compare. Performs a subtraction and sets the Zero flag if the two inputs are equivalent. The result is discarded.

- ADD : mathematical addition without carry

- ADC : mathematical addition with carry in from the control register

- SUB : mathematical subtraction. 

Flags - the flags are saved to the control register

- carry : set if the result of the mathematical operation was too big to fit in 8 bits. Note that the ALU will always calculate carry but the flag only makes sense if an unsigned mathematical operation was performed.

- overflow : set if the mathematical operation resulted in an overflow. Note that the ALU will always calculate overflow but the flag only makes sense if a 2's complement mathematical operation is being performed. In a 4 bit ALU 7 + 7 = 14 (1110) if the programmer is interpreting numbers as unsigned but if the programmer is interpreting numbers as 2's complement then the output is -2. The overflow flag can be checked for the occurrence of this type of error. 

- zero : set if the output is 0. Useful for implementing loops when combined with Branch Not Equal. e.g. decrement counter and branch if not zero.

- negative - set if the MSB is 1. Only makes sense when 2's complement notation is being used. 

Carry in - the carry flag from the control register is used by ADC. For ADD the carry in is forced to 0.

ALU left/right input buses - 8 bit left and right input buses.

ALU Output bus - 8 bit bus onto which the calculated output is placed.

NB in terms of implementation subtraction can be implemented by using XOR logic to invert the B input (XORing the input with 1 causes the input to be inverted whereas 0 leaves it unaffected) and forcing the carry input to the adder to be 1 to calculate the 2's complement (ORing the carry in from the control register with 1 if performing subtraction forces the carry to be set). This approach does not allow subtract with carry to be implemented as the carry input to the adder has been used to calculate the 2's complement. Subtraction with carry should therefore be performed using ADD and 2's complement representation.

PC Sketch #1

The 16 bit Program Counter holds the address of the next instruction to be fetched from memory. 

On fetch the PC is incremented to point to the instruction operand(s) or the next instruction to be executed.

Juno instructions consist of a single operation and zero or more operands.

In normal program flow the PC will increment unless a branch occurs in which case the PC will be loaded with the address of the instruction to be branched to.

• Enable PC count - when enabled the PC counter will increment by 1 on the next clock signal rising edge. Note that this allows the PC to be incremented in the same clock cycle as the fetch operation. 
• Enable PC out Address bus - when enabled places the value of the PC counter on the 16 bit address bus.
• Enable PC(H) out Left Bus - when enabled places the high byte of the PC counter onto the left ALU bus. This enables an effective address relative to the PC to be calculated. This relative address can be placed into the MAR for example to load A value from memory into A or loaded back into the PC to perform a PC relative branch and position independent code.
• Enable PC(L) out Left Bus - when enabled places the low byte of the PC counter onto the left ALU bus. To add or subtract from the PC the low order byte should be calculated first and to set the carry flag.
• Load PC (H) - when enabled the high byte of the PC counter is loaded with the value on the input bus from the ALU on the clock signal rising edge.
• Load PC (L) - as above but for the low byte.
• Master reset (L) - when low resets the PC counter to zero. This enables the PC to be initialised to a known value at power on and reset. When reset Juno will execute the program starting at address 0.
• Clk - the master clock signal.

Arduino - kit for testing and dev support

I have purchased a Arduino development kit to act as a test bed and toolkit to support the development of Juno.

I plan to use the Arduino to provide a slow clock signal and a clock signal that can be manually stepped one pulse at a time. 

The Arduino will also be useful as a test bed to simulate signals to individual modules to test them before integration.

It will also be useful for programming the EEPROM and simulating parts that have not been built yet in software.

The Arduino kit I ordered is from SainSmart and includes a lot of additional pieces that look very useful such as an LCD display. 

SainSmart UNO R3 Starter Kit With 19 Basic Arduino Tutorial Projects for Beginners (1602 LCD & Prototype Shield & hc-sc04 included)

http://www.amazon.co.uk/gp/r.html?R=7KIXKDF9L81B&C=11P1MGQVK7Z7I&H=SHXMN6VNFVPEUYUVMJO6RSYVZQ4A&T=C&U=http%3A%2F%2Fwww.amazon.co.uk%2Fdp%2FB00BWL1744%2Fref%3Dpe_385721_37986871_pe_364681_36330151_item

8 bit Register Sketch #1

Each general 8 bit register, e.g. A and B, has the following inputs and outputs. Other more complex registers such as the PC have additional capabilities and inputs or outputs.

• Master reset - when enabled resets the register to 0. Used to ensure the register has a known value at power on and following a reset.
• Clk - clock input. 
• Load X - when enabled the register is loaded with the input present on the input bus on the rising edge of the clock signal  
• Enable X output - when enabled the value of the register is placed on the output bus. When not enabled there is no output present. This third state allows a number of registers to share the same output bus.
• Input bus - 8 input lines. 
• Output bus - 8 output lines.

Architecture sketch #2

This version of the Juno architecture incorporates lessons learnt from architecture sketch #1

Main improvements

1. Index register - inclusion of an index register
2. All registers can act as both an input and recipient of the output from the ALU

Together these two changes enable a host of new addressing modes and capabilities.

1. Index absolute addressing mode -  effective address = memory address + index register where the memory address is a 16bit absolute address that is provided as part of the instruction. This is added to the value of the index register to calculate the effective address. Example, if IX contains the value 10 then the instruction LDA 0x1000, IX would load A with the contents of 0x1010.
2. Index base plus index -  effective address = base register + index register where the base register is a general purpose register e.g. A or B. Example LDA B, IX.
3. PC relative addressing -  effective address = PC + index register
4. Add and subtract values from the stack pointer. This capability is useful for supporting function  stack frames for creating space on the stack for a function's local variables.

This architecture also includes placeholders for supporting interrupts. It includes an interrupt line for flagging to the control unit that an interrupt has occurred and a set of lines for the interrupt number.

Notes on operation

Index addressing is implemented using the ALU to add, or subtract, from the value in the IX register and storing the result in the MDR. The value held in MDR is then placed onto the address bus. The addition or subtraction is performed first on the low order bytes and then on the high order bytes with carry.

Push and Pop operations are implemented using the ALU in a similar fashion to index addressing above but using the hard wired 1 input into the right side of the ALU.

The PC has an inbuilt counter to provide much faster operation than is possible incrementing via the ALU (which would require multiple steps to first add 1 to the least significant byte and then add any carry to the most significant byte). Jumps though are implemented by using the ALU to add, or subtract, from the PC.