Architecture v3.0 bus pin layouts

First draft layout for the two bus connectors for Architecture v3.0

• DIN 41612  
• 64 pins each

CPU bus

A1 - A8 = Left Bus (A1 LSB)
A9 - A16 = Z Bus (A9 LSB)
A17 = C_flag
A18 = V_flag
A19 = Z_flag
A20 = N_flag 
A21 - A30 = not used

A31 = GND
A32 = +5V

B1  = +5V
B2  = GND
B3  = CTRL_0  (LD_GEN_REG_1)
B4  = CTRL_1  (LD_GEN_REG_2)
B5  = CTRL_2  (LD_GEN_REG_3)
B6  = CTRL_3  (LD_GEN_REG_4)
B7  = CTRL_3  (OE_GEN_REG_1)
B8  = CTRL_4  (OE_GEN_REG_2)
B9  = CTRL_5  (OE_GEN_REG_3)
B10 = CTRL_6  (OE_GEN_REG_4)
B11 = CTRL_7  (LD_ALU_FLAGS)
B12 = CTRL_8  (INC_PC)
B13 = CTRL_9  (SEL_ALU_OR_Z)    Selects between the Z bus or ALU as input to the ALU flags. Use of the Z bus allows the flags to be loaded after previously being saved to memory.
B14 = CTRL_10 (LD_INT_ENABLED)
B15 = CTRL_11 (/OE_L_TO_R_BUS)  Used to output a register value on the data (right) bus
B16 = CTRL_12 (SEL_ALU_OP_1)    Select ALU operation
B17 = CTRL_13 (SEL_ALU_OP_2)    Select ALU operation
B18 = CTRL_14 (SEL_C_IN_1)
B19 = CTRL_15 (SEL_C_IN_2)
B20 = CTRL_16 (/OE_ALU)    Place ALU output onto the Z bus.
B21 = CTRL_17 (ALU_INV_R)  Invert the ALU right input. Used to perform subtraction using the adder
B22 = CTRL_18 
B23 = CTRL_19 
B24 = CTRL_20 
B25 = ALU_OUT_V    V output from ALU
B26 = ALU_OUT_C    C output from ALU
B27 = ALU_OUT_Z    Z output from ALU
B28 = ALU_OUT_N    N output from ALU  
B29 - B32 = not used

External bus

A1 - A16 = Address Bus (A1 LSB)
A17 - A24 = Data Bus (A17 LSB)     aka the ALU right bus
A25 = Clk
A26 = Inv_Clk
A27 = read
A28 = write
A29 = not used
A30 = not used
A31 = GND
A32 = +5V

B1 = + 5V
B2 = GND
B3 = Interrupt
B4 = IRQ_0
B5 = IRQ_1
B6 = IRQ_2
B7 = IRQ_3
B8 - B32 = not used

Architecture v3.0

Version 3.x of Juno incoporates yet more major changes to the physical architecture of the system.

The two primary changes are the use of two physical buses and switching from through the hole (DIP) ICs to SMD (SOIC)

The two physcial buses are

• CPU bus - contains CPU specific signals such as  CPU control signals. All CPU cards connect to this bus and the external bus.
• External bus - contains CPU external signals. All CPU and non-CPU boards connect to this bus.

 CPU bus

The CPU bus carries signals which are internal to the CPU and each CPU board connects to the common CPU bus via a single DIN41612 64 pin connector. The signals carried on the common CPU bus include

• CPU Left Bus (ALU right input)
• CPU Z Bus (ALU output)
• CPU control signals e.g. load register etc
• Status Register - ALU flags V, C, Z & N and the status flags Interrupts Enabled and Supervisor Mode 
• CPU clocks - non-inverted and inverted clock signals
• CPU reset
• Power
• misc. board to board signals as required 

Common External bus

The common External bus carries signals which are required external to the CPU and each external board connects to the bus via a single DIN41612 64 pin connector. The signals carried on the common external bus include

• Address bus
• Data bus (the data bus also acts as the ALU right bus)
• External control signals e.g. read, write
• External clocks 
• Power
• Interrupts

 

Standard Physical board design 

Notes on physical PCB board design

• Board size 160mm * 100mm
• CPUBUS position 0.1 1.95 (Eagle package MAB64)

• EXTBUS position 6.2 1.95 (Eagle package MAB64)
• 4 * power supply de-coupling caps 10uF (Eagle package E5-5)
• Add a title 'Juno PC <board>' (Eagle layer tDocu, vector font, size 0.07, ratio 8%)

Eagle PCB design setup

Notes on Eagle PCB design

• Design Rule - eC_2Layer_PClass6_BaseCopperO18_eCDefault
• Minimum width 0.15mm
• Net classes
• default 0.15mm
• PWR 0.20mm
• Bottom layer flood fill GND

 SOIC

A Small Outline Integrated Circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30–50% less than an equivalent dual in-line package (DIP), with a typical thickness that is 70% less. They are generally available in the same pin-outs as their counterpart DIP ICs. The convention for naming the package is SOIC or SO followed by the number of pins.