Architecture v3.0

Version 3.x of Juno incoporates yet more major changes to the physical architecture of the system.

The two primary changes are the use of two physical buses and switching from through the hole (DIP) ICs to SMD (SOIC)

The two physcial buses are

• CPU bus - contains CPU specific signals such as  CPU control signals. All CPU cards connect to this bus and the external bus.
• External bus - contains CPU external signals. All CPU and non-CPU boards connect to this bus.

 CPU bus

The CPU bus carries signals which are internal to the CPU and each CPU board connects to the common CPU bus via a single DIN41612 64 pin connector. The signals carried on the common CPU bus include

• CPU Left Bus (ALU right input)
• CPU Z Bus (ALU output)
• CPU control signals e.g. load register etc
• Status Register - ALU flags V, C, Z & N and the status flags Interrupts Enabled and Supervisor Mode 
• CPU clocks - non-inverted and inverted clock signals
• CPU reset
• Power
• misc. board to board signals as required 

Common External bus

The common External bus carries signals which are required external to the CPU and each external board connects to the bus via a single DIN41612 64 pin connector. The signals carried on the common external bus include

• Address bus
• Data bus (the data bus also acts as the ALU right bus)
• External control signals e.g. read, write
• External clocks 
• Power
• Interrupts

 

Standard Physical board design 

Notes on physical PCB board design

• Board size 160mm * 100mm
• CPUBUS position 0.1 1.95 (Eagle package MAB64)

• EXTBUS position 6.2 1.95 (Eagle package MAB64)
• 4 * power supply de-coupling caps 10uF (Eagle package E5-5)
• Add a title 'Juno PC <board>' (Eagle layer tDocu, vector font, size 0.07, ratio 8%)

Eagle PCB design setup

Notes on Eagle PCB design

• Design Rule - eC_2Layer_PClass6_BaseCopperO18_eCDefault
• Minimum width 0.15mm
• Net classes
• default 0.15mm
• PWR 0.20mm
• Bottom layer flood fill GND

 SOIC

A Small Outline Integrated Circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30–50% less than an equivalent dual in-line package (DIP), with a typical thickness that is 70% less. They are generally available in the same pin-outs as their counterpart DIP ICs. The convention for naming the package is SOIC or SO followed by the number of pins.