8 bit Register Sketch #1

Each general 8 bit register, e.g. A and B, has the following inputs and outputs. Other more complex registers such as the PC have additional capabilities and inputs or outputs.

• Master reset - when enabled resets the register to 0. Used to ensure the register has a known value at power on and following a reset.
• Clk - clock input. 
• Load X - when enabled the register is loaded with the input present on the input bus on the rising edge of the clock signal  
• Enable X output - when enabled the value of the register is placed on the output bus. When not enabled there is no output present. This third state allows a number of registers to share the same output bus.
• Input bus - 8 input lines. 
• Output bus - 8 output lines.