Overflow flag implemented using an 8:1 multiplexer

The overflow flag is used to indicate an error condition when adding, or subtracting, two's complement numbers. The error indicates that the result does not fit within the number of ALU bits and is therefore incorrect.
The overflow flag is different to the carry flag which indicates that a mathematical carry or borrow has been generated out of the most significant bit.

In a two's complement number the most significant bit indicates whether the number is negative or positive. Zero indicates positive and one indicates negative. When adding two's complement positive numbers (msb is 0) the result should be positive (msb 0) likewise when adding two negative numbers (msb is 1) the result should be negative (msb 1).

In an 8 bit ALU adding 127 and 127 gives 254 which in binary is 1111 1110. But if two's complement notation is being used then the output is not interpreted as 254 but -2.This error occures because the result is two large to fit within 8 bits and has overflowed.

It is important to understand that the overflow flag is set for every addition but it only makes sense when two's complement notation is being used. If two's complement representation is not being used it should be ignored.

The calculation of the overflow flag for addition is given below. Within Juno subtraction is performed using addition therefore we only need to calculate overflow for addition.

Inputs  Outputs
A B Z   Overflow Flag
0 0 0   0
0 0 1   1 (adding two positives should be positive)
0 1 0   0
0 1 1   0
1 0 0   0
1 0 1   0
1 1 0   1 (adding two negatives should be negative)
1 1 1   0


The calculation of the overflow flag can be done in logic as shown below






But this would require a number of logic chips of different types. An alternative approach is to implement the logic using a single 8:1 multiplexer such as the 74HC251.The 8:1 multiplexer has three select inputs(S0,S1,S2) which correspond to A, B and Z above and are used to select one of the eight inputs to be the output. By appropriately hard wiring the eight inputs high or low it is possible to create the logic table above and implement the overflow logic using a single IC.

The table below shows how the input values need to be set. 

A  B  Z   
S2 S1 S0  input  value
0  0  0   I0     0
0  0  1   I1     1
0  1  0   I2     0
0  1  1   I3     0
0  0  0   I4     0
1  0  0   I5     0
1  0  1   I6     0
1  1  0   I7     1
1  1  1   I8     0