CPU register boards and ALU block diagram

The following CPU block diagram shows the two register boards and the ALU.

CPU register board and ALU block diagram

ALU Design - 2.1

Changes from v1.x

• Updated to the v2.0 Architecture and the use of a dedicated common CPU bus for the CPU boards
• The three boards of the v1 ALU have been combined into a single board

Schematics

The General Register Board design is split across four schematics

• Common CPU bus connector
• ALU Operations
• ALU flags
• Caps

Common CPU bus connector

The common CPU bus connector is shown below.

Common CPU Bus connector

ALU Operations

The ALU can perform 3 mathematical operations and 3 logical operations.

• AND : logical AND (left AND right)
• OR : logical OR (left OR right)
• XOR : logical XOR (left XOR right)
• ADD : mathematical addition without carry (left + right + 0)
• ADC : mathematical addition with carry in from the control register (left + right + C)
• SUB : mathematical subtraction (left - right)

The ALU performs subtraction by calculating the two's complement negative of the right input and performing an addition e.g. left + (-right)

The ALU has 4 input controls

Carry Select Control

SEL_C_IN_1 and SEL_C_IN_2 are used to select the carry input

• 0 - ALU carry input is zero
• 1 - ALU carry input is one
• 2 - ALU carry input is taken from the carry flag
• (3 - ALU carry input is zero)

Invert Right Input Control

ALU_INV_R is used to invert the right input for subtraction operations

• 0 - do not invert (input xor'd 0)
• 1 - invert (input xor'd with 1)

Operation Selection Control

SEL_ALU_OP_1 and SEL_ALU_Op_2 are used to select the ALU operation to output onto the Z bus.

• 0 - OR
• 1 - AND
• 2 - XOR
• 3 - ADD

ALU Output Enable Control

OE_ALU is used to enable the ALU output onto the Z bus

• 0 - high Z state
• 1 - output enabled

ALU Operations

ALU Flags

The ALU flags circuit calculates the Z (zero) & V (overflow). The C (carry) is calculated by the adder and the N (negative) flag is simply the Z7 output.

The overflow flag is only meaningful if two's complement numbers are being added. The output is High to indicate an overflow if the following conditions are met

• Adding two positive numbers and the result is negative; or
• Adding two negative numbers and the result is positive

If unsigned maths is being performed then the Carry flag should be checked to indicate overflow instead. 

ALU flags

The ALU Zero flag is calculated by simply OR'ing all the outputs which outputs Low if the output is zero.

The ALU flags are always calculated and it is up to the micro-code to determine when they are applicable and should be saved in the ALU flags register for inspection.

PCB board

The PCB board is shown below

ALU PCB

Parts List

Part     Value          Package      Library  Position (inch)       Orientation

C1       0.1uF          C050-030X075 rcl      (2.05 0.3)            R90
C2       0.1uF          C050-030X075 rcl      (2.6 2.5)             R180
C3       0.1uF          C050-030X075 rcl      (4.8 0.25)            R90
C4       0.1uF          C050-030X075 rcl      (1.15 1.1)            R90
C5       0.1uF          C050-030X075 rcl      (2.4 1.1)             R90
C6       10uF           E5-5         rcl      (5.75 0.25)           R90
C7       0.1uF          C050-030X075 rcl      (3.55 1.1)            R90
C8       0.1uF          C050-030X075 rcl      (4.85 1.1)            R90
C9       0.1uF          C050-030X075 rcl      (1.2 3.75)            R180
C10      0.1uF          C050-030X075 rcl      (2.6 3.75)            R180
C11      0.1uF          C050-030X075 rcl      (3.6 3.75)            R180
C12      0.1uF          C050-030X075 rcl      (4.55 3.75)           R180
C13      0.1uF          C050-030X075 rcl      (5.35 3.6)            R180
C14      0.1uF          C050-030X075 rcl      (5.35 2.6)            R180
C15      0.1uF          C050-030X075 rcl      (1.2 2.55)            R180
C16      0.1uF          C050-030X075 rcl      (3.65 2.5)            R180
C17      0.1uF          C050-030X075 rcl      (4.55 2.5)            R180
C18      0.1uF          C050-030X075 rcl      (5.35 1.4)            R180
IC1      74HC08N        DIL14        74xx-eu  (3.55 3.25)           R270
IC2      74HC32N        DIL14        74xx-eu  (2.55 3.25)           R270
IC3      74HC86N        DIL14        74xx-eu  (4.5 3.25)            R270
IC4      74ACT283N      DIL16        74xx-eu  (1.15 3.2)            R270
IC5      74HC86N        DIL14        74xx-eu  (5.3 3.1)             R270
IC6      74HC153N       DIL16        74xx-eu  (1.9 1.15)            R180
IC7      74HC153N       DIL16        74xx-eu  (0.65 1.15)           R180
IC8      74HC86N        DIL14        74xx-eu  (5.3 2.1)             R270
IC9      74HC32N        DIL14        74xx-eu  (2.55 2)              R270
IC10     74HC08N        DIL14        74xx-eu  (3.6 2)               R270
IC11     74HC86N        DIL14        74xx-eu  (4.5 2)               R270
IC12     74ACT283N      DIL16        74xx-eu  (1.15 2.05)           R270
IC13     74HC153N       DIL16        74xx-eu  (4.3 0.3)             R180
IC14     74HC153N       DIL16        74xx-eu  (3.05 1.15)           R180
IC15     74HC153N       DIL16        74xx-eu  (4.3 1.15)            R180
IC16     74HC251N       DIL16        74xx-eu  (1.5 0.35)            R180
IC17     4078N          DIL14        40xx     (5.3 0.95)            R270
X1       MAB64          MAB64        con-vg   (6.2 1.95)            R0

Register Design - Register Board One v2.1

The Register Board One has the following registers

• A - General purpose register
• IX(L) - Index Register low byte
• IX(H) - Index Register high byte
• SP(L) - Stack Pointer low byte
• SP(H) - Stack Pointer high byte
• Status Register- comprising ALU flags and CPU status flags

Changes from v1.x

• Updated to the v2.0 Architecture and the use of a dedicated common CPU bus for the CPU boards
• Compared to the v1.x register boards design the PC and MAR registers have been moved to their own separate CPU board.This was done due to the physical space constraints on a single board.

Schematics

The Register Board One design is split across four schematics

• Common CPU bus connector
• Control
• General Registers
• Status Register

Status Register

The Status Register holds four ALU operation output flags and two machine state flags. The four ALU operation flags are set when performing a mathematical operation.

• V - overflow
• C - Carry
• Z - Zero
• N - Negative

The Status Register contains two flags which indicate the system state

• Interrupts enabled - when set interrupts are enabled
• Supervisor mode - when set CPU is operating in supervisor mode

The Status Register is connected directly to the micro-code sequencer (and by a tri-state buffer to the Left Bus) and is used to implement instructions such as branching on conditions.

Status Register

The ALU flags are implemented using an Octal D type flip-flop with clk and master rest inputs (74HC273N). Unlike the 74HC574s used for the main registers the ALU flag does not require tri-stated outputs as the output is permanently required by the Micro Program Sequencer.

The ALU flags have a synchronous clear function which is controlled by /CPU_RESET.

The ALU flags are loaded by selecting the ALU_flag register via the control demux which causes the clk input to be strobed in the second half of the CPU clock cycle. The ALU flags can be loaded from either the ALU output or the Z bus selectable with by SEL_ALU_OR_Z. The intention of this design is that when a mathematical operation is being performed the ALU flags are loaded from the ALU output and when the current value of the flags needs to be preserved, for example by an interrupt service routine, they can be written to main memory and loaded back via the Z bus.

The Status flags are implemented using individual D-type flip-flops (74HC74). Individual flip-flops are required because the flags need to be set and cleared individually.

The status flags have synchronous clear function which is controlled by /CPU_RESET. The pre-set input is not used and is tied to VCC.

The status flags are set or cleared by instructing the ALU to ouput 1 or 0 on the Z bus and selecting which flag to load via the control demux which causes the strobes the flip-flop clk input to be strobed in the second half of the CPU clock cycle. This approach avoids the need for individual control signals to drive the flip-flop Preset and Clear inputs. The current value of the flags can be written to memory and loaded back via the Z bus.

Registers

The general registers are implemented using octal D-type flip-flops (74HC574). Inputs are connected to the Z Bus (ALU output bus) and the tri-state outputs are connected to the Left Bus. The schematic for the general registers is shown below.

Gerneral Registers

The register clk inputs are connected to a control decoder which strobes the selected register clk input in the second half of the clk cycle when the CPU Inverted Clock goes high.

The register /OE inputs are connected to a control decoder which asynchronously sets the selected output low. The desired register is selected at the beginning of the CPU clock cycle and being asynchronous there may be glitches in the output onto the Left Bus as the demux input select settles. For this reason the value on the Left bus is latched during the second half of the clock cycle.

Control

The selection of which register to load from the Z bus is controlled via a 3-to-8 line decoder (74HC238). Output 0 unconnected and can be used to load no register when selected. The selected output is strobed High in the second half of the CPU clock cycle when the CPU Inverted Clock goes high.

The selection of which register to output onto the Left bus is controlled via an inverting 3-to-8 decoder  (74HC138). Output 0 is not connected.

Control

Common CPU bus connector

 

Common bus connector

PCB

The PCB board is shown below

PCB board

Parts List

Exported from GeneralRegister8.brd at 04/01/2015 21:53:25

EAGLE Version 7.2.0 Copyright (c) 1988-2014 CadSoft

Assembly variant:

Part         Value          Package      Library  Position (inch)       Orientation

/OE          74HC138N       DIL16        74xx-eu  (2.3 3.5)             R180
A            74HC574N       DIL20        74xx-eu  (3.1 2.5)             R270
ALU_FLAGS    74HC273N       DIL20        74xx-eu  (0.75 0.95)           R90
ALU_OR_Z     74HC157N       DIL16        74xx-eu  (2.65 0.9)            R90
C1           0.1uF          C050-030X075 rcl      (3.15 3.1)            R180
C2           0.1uF          C050-030X075 rcl      (2.7 3.1)             R180
C3           0.1uF          C050-030X075 rcl      (2.25 3.1)            R180
C4           0.1uF          C050-030X075 rcl      (1.8 3.1)             R180
C5           0.1uF          C050-030X075 rcl      (1.35 3.1)            R180
C6           10uF           E5-5         rcl      (3.85 0.25)           R180
C7           0.1uF          C050-030X075 rcl      (2.35 0.65)           R90
C8           0.1uF          C050-030X075 rcl      (0.7 3.1)             R180
C9           0.1uF          C050-030X075 rcl      (2.8 3.45)            R90
C10          0.1uF          C050-030X075 rcl      (0.45 0.6)            R90
C11          0.1uF          C050-030X075 rcl      (2.35 1.65)           R90
C12          0.1uF          C050-030X075 rcl      (1.5 0.55)            R180
IC3          74HC244N       DIL20        74xx-eu  (0.65 2.5)            R270
IX(H)        74HC574N       DIL20        74xx-eu  (1.3 2.5)             R270
IX(L)        74HC574N       DIL20        74xx-eu  (1.75 2.5)            R270
LD           74HC238N       DIL16        paul     (1.85 1.7)            R180
SP(H)        74HC574N       DIL20        74xx-eu  (2.2 2.5)             R270
SP(L)        74HC574N       DIL20        74xx-eu  (2.65 2.5)            R270
STATUS_FLAGS 74HC74N        DIL14        74xx-eu  (1.9 0.85)            R90
X1           MAB64          MAB64        con-vg   (4.15 1.95)           R0

Architecture v2.0

Version 2.x of Juno incoporates yet more major changes to the physical architecture of the system. The primary change being the splitting of the common system bus back plane, into which all the cards connect, into two seperate busses

• Common CPU bus - into which all the CPU cards connect, and
• Common external bus - into which all external system boards connect

The v1.x Architecture had a single common bus based on a DIN41612 64 pin connector shared by all cards but this was not enough pins for all the required signals.

Common CPU bus

The common CPU bus carries signals which are internal to the CPU and each CPU board connects to the common CPU bus via a single DIN41612 64 pin connector. The signals carried on the common CPU bus include

• Left Bus (ALU left input)
• Right Bus (ALU right input)
• CPU Z Bus (ALU output)
• CPU control signals e.g. load register etc
• Status Register - ALU flags V, C, Z & N and the status flags Interrupts Enabled and Supervisor Mode 
• CPU clocks - non-inverted and inverted clock signals
• CPU reset
• Power
• misc. board to board signals as required 

Common External bus

The common External bus carries signals which are external to the CPU and each external board connects to the bus via a single DIN41612 64 pin connector. The signals carried on the common external bus include

• Address bus
• Data bus
• Control signals e.g. read, write
• External clocks 
• Power
• Interrupts