Architecture v2.0

Version 2.x of Juno incoporates yet more major changes to the physical architecture of the system. The primary change being the splitting of the common system bus back plane, into which all the cards connect, into two seperate busses

• Common CPU bus - into which all the CPU cards connect, and
• Common external bus - into which all external system boards connect

The v1.x Architecture had a single common bus based on a DIN41612 64 pin connector shared by all cards but this was not enough pins for all the required signals.

Common CPU bus

The common CPU bus carries signals which are internal to the CPU and each CPU board connects to the common CPU bus via a single DIN41612 64 pin connector. The signals carried on the common CPU bus include

• Left Bus (ALU left input)
• Right Bus (ALU right input)
• CPU Z Bus (ALU output)
• CPU control signals e.g. load register etc
• Status Register - ALU flags V, C, Z & N and the status flags Interrupts Enabled and Supervisor Mode 
• CPU clocks - non-inverted and inverted clock signals
• CPU reset
• Power
• misc. board to board signals as required 

Common External bus

The common External bus carries signals which are external to the CPU and each external board connects to the bus via a single DIN41612 64 pin connector. The signals carried on the common external bus include

• Address bus
• Data bus
• Control signals e.g. read, write
• External clocks 
• Power
• Interrupts