Status Register design v0.1

The status register consists of 4 ALU operation flags (V, C, Z & N) and two status flags, Interrupt Enable & Supervisor Mode.

The 4 ALU flags are stored in an octal D-type flip-flop 74HC273, which has common CLK and CLR inputs. The two status flags are stored in two D-type flip-flops from a 74HC74 and have individual inputs. 

When the status flag is initialised all the bits are set to zero. To enable interrupts the Interrupt Enable flag needs to be set. Setting the Operation Supervisor Mode bit indicates the CPU is operating in supervisor mode.

Inputs & Ouputs

The inputs and outputs to the Status Register are as follows:

Inputs

• RESET_LOW when low asynchronously clears the 4 ALU flags and two status flags. 
• ALU_FLAG_IN (V, C, Z, N) are connected to the ALU flag outputs on the ALU's Shifter board.
• SEL_ALU_OR_Z selects between ALU_FLAG_IN or Z bus (bits 0..3) as input to the ALU flag register. Low selects ALU_FLAG_IN as the input
• L_ALU_FLAGS when high loads the ALU Flags from the selected input
• L_ENABLEINT when pulsed high loads the Supervisor mode flag with the current value of the 4th bit of the Z bus
• L_SUPMODE when pulsed high loads the Enable interrupt flag with the current value of the 5th bit of the Z bus
• E_STATUS_REG when low outputs the Status Register onto the Left Bus
• Z bus -  bit 0 = V, 1 = C, 2 = Z, 3 = N, 4 = enable interrupt, 5 = supervisor mode

Outputs

• SEQ_STATUS directly outputs the contents of the Status Register flags to the Microcode sequencer. The Carry flag is also sent to the ALU.
• Left_bus - bit 0 = V, 1 = C, 2 = Z, 3 = N, 4 = enable interrupt, 5 = supervisor mode

Operational usage

To load the ALU flags when conducting a mathematical operation set SEL_ALU_OR_Z to low to select the input from the ALU and pulse L_ALU_FLAGS high to load the flags.

To set or clear the Interrupt Enable flag set bit 4 on the Z bus and pulse the L_ENABLEINT high to load the flag. To set or clear the Supervisor Mode flag use bit 5. 

To ouput the Status Register to the left bus, for example as part of an operation to save to memory, set E_STATUS_REG low. At all other times the High Impedence state should be selected by setting E_STATUS_REG high. 

To load the Status Register from the  Z bus, for example as part of an opertation to load from memory, set SEL_ALU_OR_Z high to select the input from the Z Bus and pulse L_ALU_FLAGS, L_SUPMODE and L_ENABLEINT high.

Circuit Schematic

Status Register v0.1 schematic

PCB Board Layout

Status Register PCB layout

 

Parts list

Part            Value          Device          Package      Library  Sheet

/OE_REG                        PINHD-1X8       1X08         pinhead  1
ALU-LBUS                       PINHD-1X8       1X08         pinhead  1
ALU-RBUS                       PINHD-1X8       1X08         pinhead  1
ALU-ZBUS                       PINHD-1X8       1X08         pinhead  1
ALU_FLAG_IN                    PINHD-1X4       1X04         pinhead  1
C1              0.1uF          C-EU050-030X075 C050-030X075 rcl      1
C2              0.1uF          C-EU050-030X075 C050-030X075 rcl      1
C13             0.1uF          C-EU050-030X075 C050-030X075 rcl      1
C14             0.1uF          C-EU050-030X075 C050-030X075 rcl      1
C15             0.1uF          C-EU050-030X075 C050-030X075 rcl      1
C16             0.1uF          C-EU050-030X075 C050-030X075 rcl      1
C17             10uF           CPOL-EUE5-5     E5-5         rcl      1
DBUS                           PINHD-1X8       1X08         pinhead  1
IC1             74HC244N       74HC244N        DIL20        74xx-eu  1
IC2             74HC244N       74HC244N        DIL20        74xx-eu  1
IC3             4515N          4515N           DIL24-6      45xx     1
IC4             4514N          4514N           DIL24-6      45xx     1
IC7             74HC273N       74HC273N        DIL20        74xx-eu  1