ALU Sketch #2

This is the second design for the Juno ALU which includes a shifter to support multiplication operations. The NOT operation has been removed as it can be simulated by performing an XOR with all 1s.  

The ALU takes its input from the left and right buses and placed the calculated output on the ALU out bus. The output is not synchronised to the clock and therefore follows the inputs and will fluctuate for a period as both the inputs and internal logic stabilise.

The ALU additionally outputs a number of flags indicating carry, overflow, zero, negative conditions that are stored in the control register

Operation select - the ALU supports many mathematical and logical functions selected via the operation select control lines.

• AND : logical AND (left AND right)
• OR : logical OR (left OR right)
• XOR : logical XOR (left XOR right)
• ADD : mathematical addition without carry (left + right + 0)
• ADC : mathematical addition with carry in from the control register (left + right + C)
• SUB : mathematical subtraction (left - right)
• ROL : rotate  left. Bit 1 is filled with bit 0 etc. Bit 0 is filled with bit 7. 
• ROR : rotate right. Bit 2 is filled with bit 3. Bit 7 is filled with bit 0.
• ASL: Arithmetic shift left. All bits shifted one place to the left and bit 0 is set to 0 and bit 7 is placed in the carry flag. The effect of the operation is to multiply by 2 (ignoring 2's complement considerations)
• ASR : Arithmetic shift right. All bits shifted one place to the right and bit 7 is set to 0 and bit 0 is placed in the carry flag. The effect of the operation is to divide by 2 (ignoring 2's complement considerations)

Additional operations can be implemented in micro-code by re-using these basic operations:

• CMP : logical compare. Compares the two inputs and sets the Zero flag if equivalent. The operation is implemented using XOR but the micro-code does not save the result to a register and is discarded. 

Flags - the flags are saved to the control register

• Carry : set if the result of the mathematical operation was too big to fit in 8 bits. Note that the ALU will always calculate carry but the flag only makes sense if an unsigned mathematical operation was performed.
• Overflow : set if the mathematical operation resulted in an overflow. Note that the ALU will always calculate overflow but the flag only makes sense if a 2's complement mathematical operation is being performed. In a 4 bit ALU 7 + 7 = 14 (1110) if the programmer is interpreting numbers as unsigned but if the programmer is interpreting numbers as 2's complement then the output is -2. The overflow flag can be checked for the occurrence of this type of error. 
• Zero : set if the output is 0. Useful for implementing loops when combined with Branch Not Equal. e.g. decrement counter and branch if not zero.
• Negative - set if the MSB is 1. Only makes sense when 2's complement notation is being used. 

Carry in - the carry flag from the control register is used by ADC. For ADD the carry in is forced to 0.

ALU left/right input buses - 8 bit left and right input buses.

ALU Output bus - 8 bit bus onto which the calculated output is placed.

Subtraction is implemented by using XOR logic to invert the B input (XORing the input with 1 causes the input to be inverted whereas 0 leaves it unaffected) and forcing the carry input to the adder to be 1 to calculate the 2's complement (ORing the carry in from the control register with 1 if performing subtraction forces the carry to be set). This approach does not allow subtract with carry to be implemented as the carry input to the adder has been used to calculate the 2's complement. Subtraction with carry should therefore be performed using ADD and 2's complement representation.