The processor hardware can only address 65,536 bytes therefore paging is used to move pages of memory in and out of the processor address space. The processor always 'sees' the memory as 16K of ROM and 48K of RAM.
The ZX Spectrum +2 memory map is shown below. The first 16K is ROM which can have either ROM 0 or ROM 1 paged in to position. RAMs 2 and 5 are fixed in position and any RAM page can be paged into position RAM 0 - 7 (16 KB in size).
Memory banks 1,3,5 and 7 are contended, which reduces the speed of memory access in these banks.
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The +2 memory map |
- ROM 0 - 128k editor and menu system
- ROM 1 - 48K BASIC
- RAM 5 - the normal screen
- RAM 7 - shadow screen
Screen memory layout
The RAM 5 normal screen memory layout is as follows![]() |
RAM 5 bank screen memory layout |
Paging
Paging is controlled by performing I/O writes to ports 0x7ffd. The paging logic decodes the address bus partially (uses A15 and A1 lines only), so the exact port is 0xxx xxxx xxxx xx0x. The bits are described in the table below:
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Port 0x7ffd |
An example of a typical bank switch on the 128 is:
LD A,(0x5b5c) ;Previous value of port held somewhere convinient
AND 0xf8
OR 4 ;Select bank 4
LD BC,0x7ffd
DI
LD (0x5b5c),A
OUT (C),A
EI
The principle is the same for all bank switching: change only the bits you need to.Clear command
If you do wish to reserve memory for machine code so that it is not used by BASIC, then issue the command CLEAR n, where n is the last byte you wish to be available to BASIC. So, if you want your machine code to sit at address &8000 in the memory map, then issue the command:
| CLEAR 32767 |