ALU Shift & Flag Design v0.1

The ALU Shift & Flag board allows the output of the ALU to be optionally shifted left or right and calculates the flag outputs.

The shift operations supported are

• No shift
• Rotate Right - set carry to bit 0, move all bits one place to the right and set bit 7 to carry input
• Rotate Left - set carry to bit 7, move all bits one place to the left and set bit 0 to carry input
• Arithmetic Shift Right - set carry to bit 0, move all bits one place to the right and set bit 7 to zero
• Arithmetic Shift Left - set carry to bit 7, move all bits one place to the left and set bit 0 to zero 
• Shift Right fill with 1 - set carry to bit 0, move all bits one place to the right and set bit 7 to one 
• Shift Left fill with 1 - set carry to bit 7, move all bits one place to the left and set bit 0 to one 

For information on how to use the Rotate and Arithmetic shift operations to perform multi-byte division and multiplication see CPU multi-byte mathematical operations.

The Shift Right and Shift Left fill with 1 operations are not of mathematical use but are supported as a consequence of the design. 

The ALU flags supported are

• Zero Flag (Z) - set to 1 if the output of the ALU is zero
• Overflow Flag (V) - set to 1 if addition or subtraction has resulted in an overflow. The flag output is  always calculated but only makes sense when a 2's complement addition or subtraction is being performed. 
• Negative Flag (N) - set to 1 if the 7th bit of the ALU result is 1. The Negative flag output is always calculated but only makes sense when 2's complement numbers are being used by the programmer. 
• Carry Flag - set to 1 if a carry has occurred. The Carry flag is always calculated but only makes sense when an addition or subtraction operation is being performed. NB the value of carry is controlled by the CSEL inputs. To select the carry from the adder the CSEL inputs need to be set to 3.

The Eagle schematic can be downloaded here

ALU Flag and Shifter schematic

The Inputs are as follows
INPUT[0..3] - output from the first ALU board processing bits 0..3

• I0 - bit 0 of the ALU result
• I1 - bit 1
• I2 - bit 2
• I3 - bit 3

INPUT[4..7] -  ouput from the second ALU board processing bits 4..7. Includes various other inputs from the second ALU board.

• I4 - bit 4
• I5 - bit 5
• I6 - bit 6
• I7 - bit 7
• ADDERCOUT - carry out from the adder
• L7 - the Left Bus bit 7 input to the ALU. Used for calculating overflow.
• R7 - the Right Bus bit 7 input to the ALU. Used for calculating overflow. 
• CIN - the carry input to the ALU. Used in shift operations.

 CONTROL - control inputs

• SHIFT SEL0 - combined with SHIFT SEL1 selects the shift operation performed
• SEL1 | SEL0
• 00 = no shift
• 01 = shift right
• 10 = shift left
• 11 = not used (results in output of zero)

• SHIFT SEL1 - combined with SHIFT SEL0
• CSEL0- combined with CSEL1 selects the value to use for carry
• CSEL1 | CSEL0
• 00 = Carry in from the status register
• 01 = 0 (force the value of carry to 0)
• 10 = 1 (force the value of carry to 1)
• 11 = Adder Carry Out

The outputs are as follows

FLAG_OUTPUT

• Overflow flag
• Cout - Carry Out (NB dependent upon the CSEL control)
• Zero Flag 
• Neg Flag  - Negative flag

SHIFT_OUTPUT - ALU output onto the Z bus

• Z0..7 - bits 0 to 7

The PCB board layout can be downloaded here

ALU Flag and Shifter PCB layout

EDIT - the Flag Outputs are labelled incorrectly on the silk screen and should be like this

The parts list

Exported from ShifterAndFlagLogicv0.1.brd at 10/11/2013 21:48:37

EAGLE Version 6.5.0 Copyright (c) 1988-2013 CadSoft

Assembly variant:

Part         Value          Package      Library  Position (inch)       Orientation

C1           10uF           E5-5         rcl      (0.9 0.35)            R90
C2           0.1uF          C050-030X075 rcl      (1.35 2.25)           R270
C4           0.1uF          C050-030X075 rcl      (2 0.35)              R270
C5           0.1uF          C050-030X075 rcl      (3 1.4)               R270
C6           0.1uF          C050-030X075 rcl      (1.35 1.3)            R270
C7           0.1uF          C050-030X075 rcl      (0.35 0.55)           R270
C8           0.1uF          C050-030X075 rcl      (2 1.3)               R270
C9           0.1uF          C050-030X075 rcl      (2 2.25)              R270
C10          0.1uF          C050-030X075 rcl      (1.1 1.6)             R90
CONTROL      4              1X04         pinhead  (1.45 0.2)            R180
FLAG_OUTPUT  4              1X04         pinhead  (2.85 0.2)            R0
IC1          74HC153N       DIL16        74xx-eu  (2.3 2.7)             R90
IC2          74HC153N       DIL16        74xx-eu  (0.7 1.95)            R270
IC3          74HC251N       DIL16        74xx-eu  (0.7 1)               R90
IC4          74HC153N       DIL16        74xx-eu  (1.65 2.7)            R90
IC5          74HC153N       DIL16        74xx-eu  (2.3 1.75)            R90
IC6          74HC153N       DIL16        74xx-eu  (1.65 1.75)           R90
IC7          74HC153N       DIL16        74xx-eu  (2.3 0.8)             R90
IC10         4078N          DIL14        40xx     (3.3 1.8)             R90
INPUT[0..3]  8              1X08         pinhead  (0.2 2.3)             R270
INPUT[4..7]  8              1X08         pinhead  (0.2 1.45)            R270
POWER                       1X02         pinhead  (0.6 0.25)            R180
SHIFT_OUTPUT 8    

Bus control notes

A bus connects together multiple devices so that they can talk to one another through shared communication lines. Only one device can write to the bus, drive it, at any point in time but multiple devices can simultaneously read from it. 

A tri-state device is one that has a third output state in addition to 0 and 1. This third state is a high impedance state called Hi-Z which has the effect of disconnecting the device from the circuit. This Hi-Z state can be used to disconnect device outputs from the bus and allow one device to drive the  bus. Tri-state devices commonly have an /Output Enable which when asserted forces the devices output into the Hi-Z state.

One method of ensuring only one device is driving the bus at a time is to connect the /OE controls of all the tri-state devices to a decoder and use the decoder to select which device is enabled. All other devices will be forced into their high impedance Z state. This is a fairly fool proof method and there are decoders that will 'break before make' when switching between devices.

As the /OE is active low an inverting decoder needs to be used so that the selected output is low and all the other outputs are high.

A single 3-to-8 decoder can be used to select between 8 devices connected to a bus. If control of more than 8 devices is required two or three decoders can be chained together e.g. to create a 4-to-16 decoder.

A similar method can be used to select between multiple devices that can read from the bus. Assuming the devices latch their value from the bus on the next rising edge of the clock signal a decoder combined with AND gates can be used to 'arm' the clock input of the selected device so that only one of the devices sees the rising clock on it's clock input and reads from the bus.

Unlike ensuring that only one device is driving the bus at a time using a decoder to select between devices to read from the bus is not an electrical necessity but simply a convenience as we only need to write to one device at a time and it reduces the number of control lines required.

A transceiver such ad the 74HC245 is a bus driving device with 3-state outputs in both directions. 

74 series Flip Flop notes

The following are different 74 series flip flops.

• 74 - two independent D type flip flops with individual D, preset, clear and clock inputs. A low level at the preset or clear sets or resets the flip flop irrespective of the D or clock. When preset and clear are disabled by being high the flip flop is set to the value of the D input on the positive clock edge.
• 175 - four D type flip flops with individual D inputs and both Q and /Q outputs. Common clock and -master reset inputs load and reset all flip flops simultaneously. 
• 273 - octal edge triggered D type flip flops with Individual D inputs and Q outputs. Common clock and /master reset inputs load and reset all flip flops simultaneously. 
• 373 - octal transparent latch D type flip flops with 3-state outputs. A common Latch Enable (LE) enables all flip flops and a common Output Enable (/OE) enables all the outputs.The 573 has a more convenient pin arrangement.
• 374 - octal edge triggered D type flip flops with 3-state outputs. Common clock loads all flip flops simultaneously and a common Output Enable (/OE) enables all the outputs. The 374 does not have a seperate input enable, see 377.
• 377 - octal edge triggered D type flip flops. Common clock loads all flip flops simultaneously when input enable (date enable) is low. The 377 does not have 3-state output.
• 533 - Functionally the same as 373 but with inverting outputs.
• 563 - Functionally the same as 373 but with inverting outputs and a more convenient pin arrangement. 
• 564 - Functionally the same as the 574 but has inverting outputs.
• 573 - Functionally the same as 373 but with a more convenient pin arrangement.
• 574 - Functionally the same as the 374 but has a more convenient pin arrangement.

ALU Design v0.2

The ALU Design v0.2 is a slight variation on the previous ALU 0.1 design. 

The modification adds the Carry IN from the ALU board's input buses to the board's output bus so that Cin can form part of the input into the shifter and flags board. Cin is used by the shifter when shifting.

The Eagle CAD schematic for ALU Design v0.2 can be downloaded here.

The Eagle CAD board for ALU Design v0.2 can be downloaded here.

Post manufacture of the board I realised it would be better for the OR and AND controls to be swapped around so that OR is selected by the control input 00 rather than AND. This is so that zero in the microcode can be used when the intention is to pass a value straight through the ALU. Given the pin out of the AND and OR ICs are the same it is a simple job to just swap the ICs around.

Control input

The control input consists of 8 signals

• C0 (lsb) -  Combined with C1 used to select ALU operation to output; 00 = OR, 01=AND, 10=XOR, 11=ADDER
• C1 - see above
• CIN - Carry input from the Control Register
• LBUSINPUTSELECT - select between the external left bus (L) or hardcoded zero (H) for the ALU's left input
• RBUSINPUTSELECT - select between the external right bus (L) or hardcoded zero (H) for the ALU's right input
• CINPUTSEL0 - combined with CINPUTSEL1to select the carry input into the adder; 00 = 0, 01=1, 10 = CIN, 11 = 0
• CINPUTSEL1 - see above
• INVB (msb) - If enabled (H) inverts the ALU's right input. Used for performing subtraction. 

Data Input

There are two bus data inputs consisting of 4 bits each, bits 0 to 3.  

1. L_0 (lsb) - left bus bit 0
2. L_1 - left bus bit 1
3. L_2 - left bus bit 2
4. L_3 - left bus bit 3
5. R_0 - right bus bit 0
6. R_1 - right bus bit 1
7. R_2 - right bus bit 2
8. R_3 (msb) - right bus bit 3

Ouput

The output consists of 8 bits 

1. Z0 - output bus bit 0
2. Z1 - output bus bit 1
3. Z2 - output bus bit 2
4. Z3 - output bus bit 3
5. Cout - Carry out from the adder. NB the carry is always calculated but only makes sense when an Add or Subtract operation is being performed
6. L_3 - left input bit 3 pass through. This is used by the down stream Shifter and Flag board to calculate the overflow flag.
7. R_3 - right input bit 3 pass through. 
8. Cin - pass through of Cin to the down stream Shifter and Flag board.

The three pass through outputs are a convenience as they make the physical connection to the Shifter and Flag board simpler as all the inputs are gathered together and can be connected with a single 8 line ribbon cable from the second ALU board.